1076-2000 IEEE Standard VHDL Language Reference Manual by PDF

ISBN-10: 0738119482

ISBN-13: 9780738119489

VHSIC Description Language (VHDL) is outlined. VHDL is a proper notation meant to be used in all stages of the production of digital structures. since it is either desktop readable and human readable, it helps the improvement, verification, synthesis, and checking out of designs; the conversation of layout info; and the upkeep, amendment, and procurement of undefined. Its basic audiences are the implementors of instruments aiding the language and the complex clients of the language.

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Example text

Any TIME value whose absolute value is smaller than this limit is truncated to zero (0) time units. 6) to select a secondary unit of type TIME as the resolution limit. Furthermore, an implementation may restrict the precision of the representation of values of type TIME and the results of expressions of type TIME, provided that values as small as the resolution limit are representable within those restrictions. It is an error if a given unit of type TIME appears anywhere within the design hierarchy defining a model to be executed, and if the position number of that unit is less than that of the secondary unit selected as the resolution limit for type TIME during the execution of the model.

6). — For an interface object declared with a subtype indication that defines a constrained array subtype, the index ranges are defined by that subtype or subnature. 2), the index ranges are obtained from the corresponding association element in the applicable subprogram call. 2), the index ranges are obtained as follows: The directions of the index ranges of the formal parameter are that of the type of the formal; the high and low bounds of the index ranges are respectively determined from the maximum and minimum values of the indices given in the association elements corresponding to the formal.

If, however, there are multiple access paths to such a parameter (for example, if another formal parameter is associated with the same actual parameter), then the value of the formal is undefined after updating the actual other than by updating the formal. A description using such an undefined value is erroneous. 2 Signal parameter For a formal parameter of class signal, references to the signal, the driver of the signal, or both, are passed into the subprogram call. 100 For a signal parameter of mode in or inout, the actual signal is associated with the corresponding formal signal parameter at the start of each call.

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1076-2000 IEEE Standard VHDL Language Reference Manual


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